Indirect memory accesses are part of a code base in many applications such as control code applications, video encoder applications, video decoder applications and baseband 3GPP Long Term. Evolution applications. A common example of an indirect memory access in software is:
Char D,C;
Array B[100];
D=B[C].
To retrieve data for the character D, a digital signal processor (i.e., DSP) core performs the following operations:
1. Read a value of the character C from the memory,
2. Add the value of character C to a start address of the array B to create a next address, and
3. Read a value of the character D from the memory stored at the next address.
The indirect memory access operations take a considerable number of cycles when executed on modern DSP cores. A reason for the cycle count is a pipeline latency from receiving the value C from the memory, calculating the next address from the value C and using the next address to access the memory for the value D.
Referring to FIG. 1, a block diagram of a conventional indirect memory access design 10 is shown. Consider a conventional DSP core pipeline 16 having an address generation stage (i.e., stage G), an address to memory stage (i.e., stage A), a memory access stage (i.e., stage C) and a sample memory stage (i.e., stage S). Register files 12a-12b are used to store initial information used to address a memory 14 in the stage G. Once the address for the value C is generated in the stage G and stored in a register ADDRESS, three cycles (i.e., stages A, C and S) are used to return the value C from a line in the memory 14 to the DSP core. The next address is subsequently calculated in the stage G in another cycle and stored in the register ADDRESS. Finally, three more cycles (i.e., stages A, C and S) are used to return the value D from the memory 14 to a register in the DSP core.
It would be desirable to implement low access time indirect memory accesses.